`include "cpu_def.vh"

module decoder(
  input [31:0] instr,

  output [ 4:0] rf_raddr_0,
  output [ 4:0] rf_raddr_1,
  output [ 4:0] rs        ,
  output [ 4:0] rt        ,
  output [ 4:0] rd        ,
  output [ 4:0] sa        ,
  output [31:0] simm      ,
  output [31:0] uimm      ,
  output [ 2:0] sel       
);

  assign rf_raddr_0 = instr[`INSTR_RS];
  assign rf_raddr_1 = instr[`INSTR_RT];

  assign rs          = instr[`INSTR_RS];
  assign rt          = instr[`INSTR_RT];
  assign rd          = instr[`INSTR_RD];
  assign sa          = instr[`INSTR_SA];
  assign simm        = {{16{instr[15]}}, instr[`INSTR_IMM]};
  assign uimm        = {16'h0, instr[`INSTR_IMM]};
  assign sel         = instr[`INSTR_SEL];

endmodule